? 2004 california micro devices corp. all rights reserved. 11/01/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 1 pacvga201 vga port companion circuit features ? seven channels of esd protection for all vga port connector pins ? meets iec-61000-4-2 level-4 esd requirements (8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines, 4pf typical ? ttl to cmos level-trans lating buffers with power down mode for hsync and vsync lines ? three power supplies for design flexibility ? compact 16-pin qsop package ? lead-free version available applications ? esd protection and termination resistors for vga (video) port interfaces ? desktop pcs ? notebook computers ? lcd monitors product description the pacvga201 provides seven channels of esd protection for all signal lines commonly found in a vga port. esd protection is implemented with current-steer- ing diodes designed to safely handle the high surge currents encountered with iec-61000-4-2 level-4 esd protection (8kv contact di scharge). when a channel is subjected to an electrostatic discharge, the esd cur- rent pulse is diverted via t he protection diodes into the positive supply rail or ground where it may be safely dissipated. separate positive supply rails are provided for the video, ddc_out and sync channels to facilitate interfacing with low-voltage video controller ics and to provide design flexibility in multiple-supply-voltage environments. an internal diode (d 1 , in schematic below) is provided such that v cc2 is derived from v cc3 (v cc2 does not require an external power supply input). in applications where v cc3 may be powered down, diode d 1 blocks any dc current path from the ddc_out pins back to the powered down v cc3 rail via the upper esd protec- tion diodes. ( cont?d next page ) simplified electrical schematic video_1 video_2 video_3 v cc1 gnd sync_out2 gnd v cc2 v cc3 sync_out1 sync_in2 sync_in1 ddc_out2 ddc_out1 pwr_up r b r p gnd 3 4 5 6 9 10 11 13 1 8 2 7 12 14 sd2 16 sd1 15 d 1
? 2004 california micro devices corp. all rights reserved. 2 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 11/01/04 pacvga201 product description (cont?d) two non-inverting drivers provide buffering for the hsync and vsync signals fr om the video controller ic (sync_in1, sync_in2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc3 . when the pwr_up input is driven low, the sync outputs are driven low and the sync inputs can float: no current will be drawn from the vcc3 supply. the pacvga201 is housed in a 16-pin qsop pack- age and is available with optional lead-free finishing. ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. package / pinout diagram note: this drawing is not to scale. top view 16-pin qsop 1 2 3 4 14 13 12 11 5 6 7 10 9 8 15 16 sd2 sd1 sync_out2 sync_in2 sync_out1 sync_in1 ddc_out2 v cc3 v cc1 video_1 video_2 video_3 gnd pwr_up ddc_out1 v cc2 part numbering information pins package standard finish lead-free finish ordering part number 1 part marking ordering part number 1 part marking 16 qsop pacvga201q pacvga201q PACVGA201QR PACVGA201QR
? 2004 california micro devices corp. all rights reserved. 11/01/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 3 pacvga201 pin description specifications pin descriptions pins(s) name description 1v cc3 v cc3 supply pin. this is an isolated supply i nput for the two sync buffers and sd1 and sd2 esd protection circuits. 2v cc1 v cc1 supply pin. this is an isolated supply pin for the video_1, video_2 and video_3 esd protection circuits. 3 video_1 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 4 video_2 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 5 video_3 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 6 gnd ground reference supply pin. 7 pwr_up enables the sync buffers when high. when pwr_up is low the sync outputs are forced low and the inputs can be floated. 8v cc2 v cc2 supply pin. this is an isolated supply pin for the ddc_out1 and ddc_out2 esd pro- tection circuits. internally, v cc2 is derived from the v cc3 input if the v cc2 input is not con- nected to a supply voltage. 9 ddc_out1 ddc_out1 esd protection channel. 10 ddc_out2 ddc_out2 esd protection channel 11 sync_in1 sync signal buffer input. connects to the vga controller side of one of the sync lines. 12 sync_out1 sync signal buffer output. connects to the video connector side of one of the sync lines. 13 sync_in2 sync signal buffer input. connects to the vga controller side of one of the sync lines. 14 sync_out2 sync signal buffer output. connects to the video connector side of one of the sync lines. 15 sd1 esd protection channel input. 16 sd2 esd protection channel input. absolute maximum ratings parameter rating units v cc1 ,v cc2 and v cc3 supply voltage inputs [gnd - 0.5] to +6.0 v diode forward current (one diode conducting at a time) 20 ma dc voltage at inputs video_1, video_2, video_3 ddc_out1, ddc_out2 sync_in1, sync_in2 [gnd - 0.5] to [v cc1 + 0.5] [gnd - 0.5] to [v cc2 + 0.5] [gnd - 0.5] to [v cc3 + 0.5] v v v operating temperature range 0 to +70 c storage temperature range -65 to +150 c package power rating 750 mw
? 2004 california micro devices corp. all rights reserved. 4 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 11/01/04 pacvga201 specifications (cont?d) note 1: all parameters specified over standar d operating conditions unless otherwise noted. note 2: these parameters apply only to sync_in1, sync_in2 and pwr_up. note 3: these parameters apply only to sync_out1 and sync_out2. note 4: per the iec-61000-4-2 international esd standard, level 4 contact discharge method. v cc1 , v cc2 and v cc3 must be bypassed to gnd via a low impedance ground plane with a 0.2uf or greater, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pins and gnd. esd pulse c an be positive or negative with respect to gnd. applicable pins are: vide o_1, video_2, video_3, sync_out1, sd1, sync_out2, sd2, ddc_out1 and ddc_out2. all other pins are esd protected to the in dustry standard 2kv per the human body model (mil-std-883, method 3015). note 5: this parameter is guaranteed by design and characterization. electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i cc1 v cc1 supply current v cc1 = 5.0v 10 a i cc3 v cc3 supply current v cc3 = 5v; sync inputs at gnd or v cc3 ; pwr_up pin at v cc3 ; sync ouputs unloaded 10 a v cc3 = 5v; sync inputs at 3.0v; pwr_up pin at v cc3 ; sync ouputs unloaded 200 a v cc3 = 5v; pwr_up input at gnd; sync ouputs unloaded 10 a v cc2 v cc2 pin open circuit voltage v cc2 voltage internally derived from v cc3 via diode d1; no external current drawn [v cc3 -0.80] v v ih logic high input voltage v cc3 = 5v; note 2 2.0 v v il logic low input voltage v cc3 = 5v; note 2 0.8 v v oh logic high output voltage i oh = -4ma, v cc3 = 5.0v; note 3 4.4 v v ol logic low output voltage i ol = 4ma, v cc3 = 5.0v; note 3 0.4 v r b, r p resistor value pwr_up = v cc3 = 5.0v 0.5 1 2 m ? i in input current video_x pins hsync, vsync pins note 5 applies for all cases. v cc1 = 5.0v; v in = v cc1 or gnd v cc3 = 5.0v; v in = v cc3 or gnd 1 1 a a c in input capacitance on video_1, vi deo_2 and video_3 pins note 5 v cc1 = 5.0v; v in = 2.5v; measured at 1mhz v cc1 = 2.5v; v in = 1.25v; measured at 1mhz 4 4.5 pf pf t plh sync buffer l => h propagation delay c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 812ns t phl sync buffer h => l propagation delay c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 812ns t r, t f sync buffer output rise & fall times c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 7.0 ns v esd esd withstand voltage v cc1 = v cc2 = v cc3 = 5v; notes 4 & 5 8kv
? 2004 california micro devices corp. all rights reserved. 11/01/04 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 5 pacvga201 application information figure 1. typical connection diagram a resistor may be necessary between the v cc2 pin and ground if protection against a stream of esd pulses is required while the pacvga201 is in th e power-down state. the va lue of this resistor sh ould be chosen such that the extra charge deposited into the v cc2 bypass capacitor by each esd pu lse will be discharged before the next esd pulse occurs. the maximum esd repetition rate sp ecified by the iec-61000-4-2 standard is one pulse per second. when the pacvga201 is in the power-up state, an internal discharge resistor is connected to ground via a fet switch for this purpose. for the same reason, v cc1 and v cc3 may also require bypass capacitor di scharging resistors to ground if there are no other components in the system to provide a discharge path to ground. red 11 13 10 9 8 2 video connector video controller h-sync v-sync ddc_data ddc_clk blue green h-sync v-sync ddc_data ddc_clk red green blue pacvga201 ddc_out2 ddc_out1 sync_in1 sync_in2 3 video_1 video_2 video_3 4 5 vf** vf** vf** v cc1 gnd pwr_up sync_out1 sync_out2 14 12 to video 1 v cc2 v cc3 0.2uf 0.2uf sf** sf** 7 6 vf** - video emi filter sf** - sync emi filter 5v dac v cc 0.2uf sd1 sd2 16 15 gnd
? 2004 california micro devices corp. all rights reserved. 6 430 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.calmicro.com 11/01/04 pacvga201 mechanical details qsop mechanical specifications pacvga201 devices are supplied in 16-pin qsop packages. dimensions are presented below. for complete information on the qsop-16, see the california micro devices qsop package information document. * this is an approximate number which may vary. package dimensions for qsop-16 package dimensions package qsop (jedec name is ssop) pins 16 dimensions millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.81 3.98 0.150 0.157 e 0.64 bsc 0.025 bsc h 5.79 6.19 0.228 0.244 l 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs controlling dimension: inches mechanical package diagrams e d h top view l end view c e b a a1 seating plane side view 5678 1234 12 11 10 9 16 15 14 13 pin 1 marking
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